The present invention generally relates to microprocessors, and more particularly to a microprocessor which is developed by use of a piggy chip and an evaluation chip.
Generally, in a large scale integrated circuit having a one-chip structure and especially in a microprocessor, an evaluation chip is used in an initial stage of the development of the microprocessor. The evaluation chip has no mask read only memory (ROM) for storing programs. For this reason, a so-called piggy back type package which may be mounted with an external memory (piggy chip) is used. In this type of a microprocessor, the programs stored in the external memory are executed for the purpose of developing the software and carrying out function tests. When the functions satisfying a desired specification are obtainable, the development process advances to a mask data write process for writing the software into the mask ROM. The designing of the hardware portion excluding the ROM is already completed when carrying out this mask data write process. Thus, the designing of the logic, the circuit and the mask pattern is omitted for this completed hardware portion, and it is possible to produce different kinds of microprocessors having different software functions.
But in such a microprocessor, the addresses allocated for the ROM, a random access memory (RAM) and an input/output interface are fixed. That is, the so-called memory map is fixed. As a result, when mass producing a family of microprocessor chips which only differ in the memory capacities of the respective ROMs, for example, it is necessary to prepare a number of evaluation chips corresponding to a number of ROM versions. Therefore, there is a problem in that the cost of developing such a family of microprocessor chips becomes high.
FIG. 1 shows an example of a memory map of conventional microprocessor when the memory capacity of the ROM is 4 kbytes. In this case, an address region allocated for an external programmable (ROM) and the like at the time of the evaluation corresponds only to a "ROM region" shown in FIG. 1. Address regions respectively allocated for the RAM and the input/output interface are indicated as "RAM region" and I/O region". Accordingly, an evaluation chip for use in evaluating the microprocessor having the ROM with the 4 kbyte memory capacity cannot be used for an accurate evaluation of different versions of the microprocessor having ROMs with 8 kbyte and 16 kbyte memory capacities, for example, even though the hardwares of these different versions of the microprocessor excluding the ROMs are the same.
A description will now be given of the problems which are introduced when different versions of the microprocessor chip are evaluated by use of the same evaluation chip. FIGS. 2A, 2B and 2C respectively show memory maps of versions A, B and C of the microprocessor chip. As may be seen from FIGS. 2A, 2B and 2C, the ROM of the version A microprocessor chip has the smallest memory capacity, the ROM of the version B microprocessor chip has the intermediate memory capacity and the ROM of the version C microprocessor chip has the largest memory capacity. In this case, the memory map of the evaluation chip is set as shown in FIG. 3 and the addresses allocated for the ROM is matched to that of the version C microprocessor having the ROM with the largest memory capacity.
The evaluation of the version C microprocessor chip can be carried out satisfactorily by use of the evaluation chip having the memory map shown in FIG. 3 because a ROM enable signal is generated only in the memory region allocated for the ROM of the version C microprocessor chip. However, when evaluating the version A (or B) microprocessor chip by use of the same evaluation chip, a ROM enable signal is also generated in a memory region a (or b) which actually is not allocated for the ROM of the version A (or B) microprocessor chip. As a result, an accurate evaluation of the version A (or B) microprocessor chip cannot be made by use of the evaluation chip which has the memory map shown in FIG. 3.